Basic electronics fundamentals – III

The CPU bus has multiplexed lines but the system bus has separate lines for each signal. (The multiplexed CPU lines are de-multiplexed by the CPU interface circuit to form system bus).

The system clock is necessary for synchronizing various internal operations or devices in the microprocessor and to synchronize the microprocessor with other peripherals in the system.

The direct data transfer between I/O device and memory is called DMA.

When the I/O device needs a DMA transfer, it will send a DMA request signal to DMA controller. The DMA controller in turn sends a HOLD request to the processor. When the processor receives a HOLD request, it will drive its tri-stated pins to high impedance state at the end of current instruction execution and send an acknowledge signal to DMA controller. Now the DMA controller will perform DMA transfer.

The timing diagram provides information regarding the status of various signals, when a machine cycle is executed. The knowledge of timing diagram is essential for system designer to select matched peripheral devices like memories, latches, ports, etc., to form a microprocessor system.

The Software interrupts are program instructions. These instructions are inserted at desired locations in a program. While running a program, if software interrupt instruction is encountered then the processor executes an interrupt service routine.

If an interrupt is initiated in a processor by an appropriate signal at the interrupt pin, then the interrupt is called Hardware interrupt.

The Software interrupt is initiated by the main program, but the Hardware interrupt is initiated by an external device. In microprocessors, the Software interrupt cannot be disabled or masked but the Hardware interrupt except TRAP can be disabled or masked.

The TRAP is non-maskable interrupt of processor. It is not disabled by processor reset or after reorganization of interrupt.

Masking is preventing the interrupt from disturbing the current program execution. When the processor is performing an important job (process) and if the process should not be interrupted then all the interrupts should be masked or disabled. In processor with multiple ‘interrupts, the lower priority interrupt can be masked so as to prevent it from interrupting, the execution of interrupt service routine of higher priority interrupt.